1. Field of the Invention
The present invention relates to a receiver and, more particularly, to a system for synchronization of an analog signal processor in a multi-gigabit receiver system.
2. Description of Related Art
Nowadays, data is commonly transmitted wirelessly using digital modulation. Typically, a receiver receives the wireless signal, which is ultimately digitized using sampling, and then fed to a digital signal processor. Specifically, the wireless signal is received by an antenna, down converted and then sampled by a high resolution analog-to-digital converter (ADC), and finally processed by the digital signal processor (DSP).
Transmitting digital signals is efficient for data at slow speeds. For instance, transmitting using digital modulation and demodulation is preferred for data being transmitted wirelessly at less than 50 megabits per second (Mbps). When it is desired to transmit at higher speeds, i.e., higher than 50 Mbps, digital demodulation becomes undesired, as there are many problems. For instance, because there is a need for both a high-resolution, high-speed ADC and a DSP with digital demodulation, the receiver is expensive, high-power consuming, and requires an undesirable large footprint.
Instead of demodulating the wireless signal in the digital domain at high speed systems—for example, for multi-gigabit wireless transmission using an unlicensed frequency-band for high-speed data transfer between storage devices, point-to-point video, high-definition television (HDTV), and wireless personal area networking (WPAN) applications—it would be preferable to demodulate the wireless signal using analog techniques.
Specifically, QPSK (Quadrature Phase Shift Keying) can be used for optimum architecture because of higher throughput (approximately 2 bits/Hz in baseband) and less demand for signal to noise ration (SNR) per bit (approximately 10 dB for a bit error rate of 10−5). Phase shift keying can be used to digitally modulate data by changing the phase of a reference signal. In conventional architecture, however, very high-speed, high-resolution ADCs are required to sample the baseband signal and digitally enable the demodulation. In the case of multi-gigabit signal, implementation of ADCs exhibiting sampling rate more than 1 Giga-sample-per-second (Gsps) and digital functions (such as synchronization, phase and frequency tracking, ultra high-speed large-size fast Fourier transform and inverse fast Fourier transform) consume a lot of power and can cause latency issues.
For example, in the case of 7 Gbps QPSK (maximum payload possible, without filtering, with QPSK modulation within the 57-64 GHz unlicensed bandwidth), at least two ADCs exhibiting a minimum sampling at a rate of 7 Gsps are required to sample the I and Q channels (3.5 Gbps each). The result is again a large footprint, and high-power consuming system.
What is needed, therefore, is an improved system to provide a compact, robust and power-efficient analog solution for the demodulation of a multi-gigabit signal. It is to such a method, device, and system that the present invention is primarily directed.